Integrated circuits traditionally use synchronous protocols for data transfer. Existing testing and validation technologies rely heavily on cycle-by-cycle, deterministic, synchronous models.
In a massively parallel architecture or a platform-level design, the number and diversity of interacting clock domains increases. Synchronizing all of the clock domains can be prohibitive because of engineering costs, power consumption, and project-level risks. Accordingly, such architectures and designs increasingly utilize multiple asynchronous clock domains. However, it is difficult to validate or emulate a fully asynchronous architecture with industry-standard validation hardware and software.